Field of Invention
The following disclosure relates to the manufacturing of microelectronic devices, specifically but not exclusively to layers which enable the formation structures on a substrate using photolithographic techniques. In particular, the invention relates to the methods of producing materials and coatings which can be used in photolithographic applications and their subsequent etching processes to form desired structures on a substrate, and applications thereof.
Description of Related Art
To meet the demand for smaller electronic products, there is a continuing effort to increase the performance of packaged microelectronic devices while simultaneously minimizing the area of such devices on printed circuit boards.
In continued miniaturization, reducing the height and the surface area size i.e. the density of high performance devices is difficult. A method for increasing the component density of microelectronic devices, in addition to reduced line widths, is to lay one device or integrated circuit (IC) on top of another. In practice, this is achieved by electrically coupling an active circuit layer on a die to another active circuit layer on the same, or a different, die by means of an electrically conductive through substrate vias. In semiconductor industry such are most frequently called through silicon vias (TSV).
These vertical interconnects electrically couple bond-pads or other conductive elements adjacent or nearby to one side of the dies to conductive elements adjacent or nearby to the other side of the dies. Working through the back-end-of-the-line (BEOL) or the “via last method”, through silicon wafer interconnects, for example, are constructed by forming deep vias from the backside to bond-pads on the front side of the wafer, which contains most of the circuitry for the given design. The formed vias are often closed at one end, then filled with a conductive material, and after further processing the wafer in its manufacturing flow, it is eventually thinned to reduce the thickness of the final dies sufficiently to obtain a through substrate interconnect. Working though the front-end-of-the-line (FEOL) or the “via first method” the vias are formed to great extent prior to the manufacturing of designed circuitry. The “via last method” is more challenging as the vias in general are much deeper compared to those generated in the “via first method” and the formation of these include etching or laser processing through stacks of layers such as silicon and silicon oxide.
A complexity in the formation of through-substrate interconnects is in the difficulty to perform etching to give such deep, narrow holes in a substrate. These high aspect ratio vias are often formed on substrates 0.75-1.5 mm thick and should exhibit minimum amount of sidewall roughness to permit successful subsequent manufacturing steps. The closed vias can be formed by etching the holes through a pattern generated by photo lithographic techniques. The etching is predominately carried out in inductive coupled plasma (ICP) reactors where the conditions to form such vias may require considerable amount of time. Additionally, the depth of the holes is difficult to control and the etchant may damage features on substrate unless properly protected.
The vias may also be formed by laser processing holes into the substrate. Laser processing of high aspect ratio vias through the substrate is not suitable for many applications. The depths of the holes are difficult to control resulting in too shallow or deep vias. Laser processing is also a high temperature process producing hot zones which may affect neighboring structures within the wafer and requires produced residues to be removed. Hence, etching or laser processing deep, high aspect ratio holes in a substrate may be difficult in many applications.
A second complexity in the formation of the deep, high aspect ratio structures is in the pattern integrity of the structure. The patterning for a given layer is often performed by a multi-step process consisting of photo resist spin coating, photo resist exposure, photo resist development, substrate etch, and photo resist removal of a substrate. Performing etching of deep vias may require very thick photo resist during etching as the environment may cause undesirable degradation of the photo resist as well. Hence, difference in etch rates should be as large as possible between the substrate to be etched and the coating preventing the undesired etching of the substrate. Additionally, application of such thick resists may be impractical in terms of time consumed and contamination of the ICP reactor that result from the use of such thick resists. Hence the selectivity of etching of the resist used in patterning and the substrate is of great importance.
In addition, materials or hard masks, with high etch selectivity have been employed in photolithographic formation of features with a line width of 65 nm and below. As variations in line widths of the patterns during photolithographic processing can result from optical interference from light reflecting off an underlying layer on a semiconductor substrate, anti-reflective coatings (ARC) have been employed to avoid this effect. To minimize the required processing steps it is beneficial to combine the properties of the hard mask layer and the ARC in a single layer. As regards the state of the art, reference is made to US Published Patent Application No. 2008/0206578.
In view of the drawbacks with prior art in patterning and etching of materials to enable formation of deep, high aspect ratio structures and narrow line widths, there is a continued need to develop novel materials which substantially reduce degradation of the pattern forming material, improve the protection of laid out designs on a substrate and improve the manufacturing efficiency and control of deep, high aspect ratio, and other vias, holes and structures.